One of the major trends in semiconductor packaging is the effort to shrink the package outline so that the package consumes less area and less height when it is mounted onto the circuit board. Another powerful trend is the effort to achieve the outline reduction with minimum cost (both material and manufacturing cost). One of the most successful approaches has been the development of so-called “chip-scale packages”. These packages have an outline adding less than 20% to the chip area. A chip-scale package which has only the size of the chip itself, is often referred to as “chip-size package”.
Within the semiconductor memory product families, one of the most promising concepts for chip-scale packages is the so-called “board-on-chip” design. Recently, several patent applications for this design concept have been submitted, entitled “Chip-Size Integrated Circuit Package” (Serial # 9702348-5 filed in Singapore on Jul. 2, 1997, and Ser. No. 08/994,627 filed in the U.S. on Dec. 19, 1997), “Thin Chip-Size Integrated Circuit Package and Method of Fabrication” (Serial # 9800005-2 and Serial # 9800006-0 filed in Singapore on Jan. 2, 1998), “Semiconductor Device Testing and Burn-in Methodology” (Serial # 9800617-4, filed in Singapore on Mar. 25, 1998, and Serial # 9800654-7, filed in Singapore on Mar. 28, 1998), “Method of Encapsulating Thin Semiconductor Chip-Scale Packages” (filed in Singapore on Aug. 25, 1998), all assigned to Texas Instruments Incorporated. Progress has been made in reducing the area and height requirements of packages, but frustrating problems still remain in maximizing adhesion, device reliability assurance and manufacturing cost reduction.
The patent disclosure entitled “Apparatus and Method for Direct Silicon Chip Attachment to a Lead Frame” (Serial # 9800171-2 filed in Singapore on Jan. 23, 1998, and Ser. No. 09/115,160 filed in the U.S. on Jul. 14, 1998), also assigned to Texas Instruments Incorporated, describes a process to fabricate a chip-scale package by attaching a silicon chip to a printed circuit board using a metal layer and an adhesive layer, thus forming a strong attachment. The metal layer may be disposed on the printed circuit board with the adhesive layer disposed between the metal layer and the chip or the metal layer may be disposed on the chip with the adhesive layer disposed between the metal layer and the printed circuit board. Unfortunately, the process of using both and a metal layer and an adhesive layer is expensive.
In the last few years, several publications discussed principal approaches of increasing the adhesion strength. In “Polyimide Surface Characteristics for Adhesion Strength at the Interface between Polyimide and Mold Resin” (Proc. IEEE Singapore IPFA, pp. 6–10, 1993), M. Amagai et al. exposed photosensitive and non-photosensitive polyimides to reactive ion etching plasma and then encapsulated the samples in two types of thermoplastic molding resins. The authors demonstrated the advantage of breaking C—N chemical bonds by the plasma energy, making the polyimide surface very hydrophilic with an increasing density of carbonyl and carboxyl groups. They believed that the polyimide molecules are oriented parallel to the surface and that their free radicals (carbonyl and carboxyl groups) are subsequently oriented perpendicular to the polyimide surface. The results suggested that the interfacial adhesion is due to the chemical bond between the hydrogen of molding resin and the oxygen of the polyimide surface. Furthermore, the authors found that the plasma treatment increases the polyimide surface roughness. Increased contact area improves the interfacial adhesion.
Similar results of adhesion between plasma-exposed polyimide layers and epoxy molding compounds were reported by M. Amagai et al. in “The Effect of Polyimide Surface Morphology and Chemistry on Package Cracking Induced by Interfacial Delamination” (Proc. IEEE International Reliability Physics Symposium, pp. 101–107, 1994). The use of an epoxy molding resin which had enhanced rotational freedom at the molecular level (non-linear molecule) increased the adhesion and prevented interfacial delamination and package cracking.
The knowledge gained was applied to polyimide-to-metal adhesion in “The Effect of Adhesive Surface Chemistry and Morphology on Package Cracking in Tapeless Lead-on-Chip (LOC) Packages” (45th IEEE Electronic Components and Technology Conference, 1995). The LOC package is the dominant package type for centerline-bonded memory devices since the 1 Mbit DRAM; today's 64 and 256 Mbit DRAM are also packaged using the LOC technology. In the so-called “tapeless” modification, a thermoplastic adhesive layer, deposited on the protective passivation layer of the chip surface, has replaced the original double-sided adhesive tape. From the standpoint of cost reduction, this is an improvement, but still not a satisfactory solution. M. Amagai's work focused on the interfacial adhesion strength the epoxy molding compound and the adhesive surface. He found that the strength is primarily determined by the degree of bonding between the hydrogen of the epoxy molding compound and the silicone, oxygen, and fluorine of the adhesive surface. Relatively little attention was given to the adhesion between the metallic leadframe (copper, iron-nickel alloy, etc.) and the adhesive layer.
In modern chip-size packages, the lead-on-chip (LOC) concept has been replaced by the board-on-chip (BOC) concept. Little is known about maximizing the adhesion between the board and the adhesive surface, and no investigation has been performed to maximize adhesion directly between the board and the protective passivation layer of the chip surface. The goal of offering for commercial products a cost-effective, reliable method of manufacturing in high volume and with flexible, low-cost process has remained elusive, until now.
Consequently, an urgent need has arisen for assembling chip-scale semiconductor packages based on simplified, low-cost processes that result in reliable products and at the same time achieve improvements toward the goal of small outline and low profile packages. The method should be flexible enough to be applied for different semiconductor product families and a wide spectrum of design and process variations, and should allow the usage of various formulations of board materials. Preferably, these innovations should be accomplished using the installed equipment base so that no investment in new manufacturing machines is needed.